An EEPROM is provided with external input terminals such as a chip enable terminal CE, a write enable terminal WE, an output enable terminal OE, etc., to be mounted in, for instance, an information processing system, so that a writing or an erasing is carried out in a writing mode which is set by aplying high and low signals to the above terminals.
One example of modes to be set is explained in the below table.
______________________________________ TERMINAL MODE ##STR1## ##STR2## ##STR3## I/O ______________________________________ READ L H L DATA OUTPUT WRITE L L H DATA INPUT STAND-BY H NON- NON- HIGH- SPECI- SPECI- IMPEDANCE FIED FIED INHIBIT OF NON- NON- H WRITE SPECI- SPECI- FIED FIED NON- H NON- SPECI- SPECI- FIED FIED ______________________________________
In this table, the letter "H" is a high signal, and the letter "L" is a low signal. Furthermore, the letters "I/O" indicate an input and output terminal.
Even if one of the modes is correctly selected by applying the signals specified in the table to the respective terminals, an erroneous writing or an erroneous erasing is liable to occur in memory cells in the EEPROM, where a power supply is shut off or a voltage thereof is decreased outside an operation voltage range due to a failure, etc. of the system in which the EEPROM is mounted. For instance, where the stand-by mode is set in the state that a high signal is applied to the CE terminal, a low signal is applied to the WE terminal, and a high signal is applied to the OE terminal, it is assumed that a power supply voltage is abruptly decreased, so that the high signals of the CE and OE terminals are changed to be low. In this situation, it is further assumed that a capacitive load is connected to the OE terminal ten times faster than a capacitive load is connected to the CE terminal, so that a rate by which a voltage is changed from the high signal to a low signal at the CE terminal is faster than a rate of the change at the OE terminal. This results in a signal state of a writing mode in the above table momentarily. As a result, indefinite data on the I/O terminal having a state of a high impedance for the stand-by mode are erroneously written into an address of a memory cell.
For the purpose of avoiding such an erroneous writing occuring due to the decrease of the power supply voltage, a circuit for detecting the voltage decrease is generally built in an EEPROM system. The power supply voltage detecting circuit supplies a high signal at its output terminal, when a power supply voltage Vcc is larger than a predetermined voltage Vcc.sub.(INV), and a low signal at its output terminal, when the voltage Vcc is equal to or smaller than the voltage Vcc.sub.(INV). Consequently, the EEPROM is controlled to be in an inhibit state of a data writing, where the low signal is supplied from the output terminal of the detecting circuit. As a matter of course, the voltage Vcc.sub.(INV) is determined to be lower than an operating range of the power supply voltage Vcc, and is desired to be suppressed from the change thereof due to the fluctuation of an environmental temperature around the EEPROM, device parameters of transistors in fabricating the EEPROM, etc.
If it is assumed that the voltage Vcc.sub.(INV) is increased to be inside the operating range of the power supply voltage, a data writing becomes impossible even in an ordinary writing mode. On the contrary, if the voltage Vcc.sub.(INV) is set to be too low, it becomes impossible to detect the decrease of the power supply voltage Vcc precisely, so that the aforementioned erroneous writing occurs in the EEPROM.
A conventional circuit for detecting the decrease of a power supply voltage includes three Nchannel enhancement mode IGFETs (defined "NE-IGFETs" hereinafter), two N-channel depletion mode IGFET (defined "ND-IGFET" hereinafter), and an inverter, such that a high or low signal is supplied from an output terminal of the inverter dependent on a detecting result of a power supply voltage Vcc, although the structure and operation of the detecting circuit will be explained in detail later. Accordingly, an erroneous writing can be avoided in accordance with the output signal of the inverter in the detecting circuit.
However, the conventional circuit for detecting a decrease of a power supply voltage has disadvantages as follows, the cause of which will be also explained in detail later.
(1) The predetermined voltage Vcc.sub.(INV) is set to be three times a threshold voltage of the NE-IGFET. Therefore, where the threshold voltage is changed due to a temperature change by .DELTA.V.sub.THN, the predetermined voltage Vcc.sub.(INV) is changed as much as 3. .DELTA.V.sub.THN. As a result, the predetermined voltage Vcc.sub.(INV) is increased at a low temperature to be near the operating voltage range (for example, 4.5 V to 5.5 V), while the predetermined voltage Vcc.sub.(INV) is decreased at a high temperature, thereby making it difficult to detect a decrease of a power supply voltage precisely.
(2) In order that the predetermined voltage Vcc.sub.(INV) is not inside the operating voltage range at a low temperature, the predetermined voltage Vcc.sub.(INV) must be designed by considering a temperature characteristic of the threshold voltage of the NEIGFET. For this reason, the design of the circuit for detecting the decrease of a power supply voltage becomes difficult.
(3) The predetermined voltage Vcc.sub.(INV) is liable to be too low at a low temperature, thereby making it difficult to avoid an erroneous writing of the EEPROM occuring due to the decrease of the power supply voltage in a wide temperature range. Consequently, the usage temperature range of the EEPROM becomes narrow.